Artifact Evaluation in the FPGA Community

Artifact Evaluation is being adopted in the Computer Science (CS) community to further the goals of reproducible research and to improve reliability and confidence of readers in published results. The FPGA community faces specific challenges for producing reproducible results compared to other computing fields due to the use of non-standard hardware platforms.

Miriam Leeser and Suhaib Fahmy led the first Artifact Evaluation effort at FPGA 2020, and have continued to do so every year since then. FPT started AEevaluating artifacts in 2021 and has continued every year since then. FCCM isintroduced introducingartifact AEevaluation thisin year. FPL did AE last year but only for the2023. ACM TRETS papers associated with FPL. There has beenalso anintroduced issueartifact workingevaulation, with IEEE on badging, but they are working with usincluding for FCCMJournal thisTrack yearpapers for FPL and I am cautiously optimistic that their badging will improved. We have introduced AE for ACM TRETS papers associated with conferences.FPT.