# FPT Best Paper Awards

The International Conference on Field Programmable Technology (FPT) has awarded Best Paper Awards to the following papers:

#### 2025, Shanghai, China
**[
JEDI-Linear: Fast and Efficient Graph Neural Networks for Jet Tagging on FPGAs](https://ieeexplore.ieee.org/document/11363785/)**  
Zhiqiang Que, Chang Sun, Sudarshan Paramesvaran, Emyr Clement, Katerina Karakoulaki, Christopher Brown, Lauri Laatu, Arianna Cox, Alexander Tapper, Wayne Luk and Maria Spiropulu

#### 2024, Sydney, Australia

**[GraphNoC: Graph Neural Networks for Application-Specific FPGA NoC Performance Prediction](https://doi.org/10.1109/ICFPT64416.2024.11113460)**  
Gurshaant Malik and Nachiket Kapre

#### 2023, Yokohama, Japan

**[PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference](https://doi.org/10.1109/ICFPT59805.2023.00012)**  
Marta Andronic and George A. Constantinides

**[Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices](https://doi.org/10.1109/ICFPT59805.2023.00027)**  
Andrew Boutros, Fatemehsadat Mahmoudi, Amin Mohaghegh, Stephen More and Vaughn Betz

#### 2022, Hong Kong SAR
**[Cloning the Unclonable: Physically Cloning an FPGA RO PUF](https://doi.org/10.1109/ICFPT56656.2022.9974597)**  
Hayden Cook, Jonathan Thompson, Zephram Tripp, Brad Hutchings and Jeffrey Goeders

#### 2021, Virtual Conference
**[A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning](https://doi.org/10.1109/ICFPT52863.2021.9609699)**  
Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu and Masato Motomura

#### 2019, Tianjin, China
**[Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit](https://doi.org/10.1109/ICFPT47387.2019.00025)**  
Long Chung Chan, Gurshaant Malik and Nachiket Kapre

#### 2018, Naha, Japan
**[Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware](https://doi.org/10.1109/FPT.2018.00013)**  
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki and Masato Motomura

#### 2017, Melbourne, Australia
**[Synthesis of Program Binaries into FPGA Accelerators with Runtime Dependence Validation](https://doi.org/10.1109/FPT.2017.8280126)**  
Shaoyi Cheng, Qijing Huang and John Wawrzynek

#### 2016, Xian, China
**[High Density, Low Energy, Magnetic Tunnel Junction Based Block RAMs for Memory-rich FPGAs](https://doi.org/10.1109/FPT.2016.7929181)**  
Kosuke Tatsumura, Sadegh Yazdanshenas and Vaughn Betz

#### 2015, Queenstown, New Zealand
**[Energy Minimization in the Time-Space Continuum](https://doi.org/10.1109/FPT.2015.7393131)**  
Hyunseok Park, Shreel Vijayvargiya and André DeHon

#### 2014, Shanghai, China
**[Design Re-Use for Compile Time Reduction in FPGA High-Level Synthesis Flows](https://doi.org/10.1109/FPT.2014.7082746)**  
Marcel Gort and Jason Anderson

#### 2013, Kyoto, Japan
**[Maximum Flow Algorithms for Maximum Observability During FPGA Debug](https://doi.org/10.1109/FPT.2013.6718324)**  
Eddie Hung, Al-Shahna Jamal and Steven J. E. Wilton

#### 2012, Seoul, South Korea
**[iDEA: A DSP Block Based FPGA Soft Processor](https://doi.org/10.1109/FPT.2012.6412128)**  
Hui Yan Cheah, Suhaib A. Fahmy and Douglas L. Maskell

**[Graph Minor Approach for Application Mapping on CGRAs](https://doi.org/10.1109/FPT.2012.6412149)**  
Liang Chen; Tulika Mitra

#### 2011, New Delhi, India
**[VLIW-SCORE: Beyond C for Sequential Control of SPICE FPGA Acceleration](https://doi.org/10.1109/FPT.2011.6132678)**  
Nachiket Kapre and André DeHon

#### 2010, Beijing, China
**[Parallelizing FPGA placement using transactional memory](https://doi.org/10.1109/FPT.2010.5681538)**  
Steven Birk. J. Gregory Steffan and Jason H. Anderson

#### 2009, Sydney, Australia
**[American Option Pricing on Reconfigurable Hardware Using Least-Squares Monte Carlo Method](https://doi.org/10.1109/FPT.2009.5377662)**  
Xiang Tian and Khaled Benkrid

#### 2008, Taipei, Taiwan
**[Optimizing Residue Arithmetic on FPGAs](https://doi.org/10.1109/FPT.2008.4762364)**  
Haohuan Fu, Oskar Mencer and Wayne Luk

#### 2007, Kitakyushu, Japan
**[Memory Footprint Reduction For FPGA Routing Algorithms](https://doi.org/10.1109/FPT.2007.4439225)**  
Scott Y.L. Chin and Steven J.E. Wilton

#### 2006, Bangkok, Thailand
**[FPGA core watermarking based on power signature analysis](https://doi.org/10.1109/FPT.2006.270313)**  
Daniel Ziener and Jurgen Teich

#### 2005, Singapore
**[Dynamic voltage scaling for commercial FPGAs](https://doi.org/10.1109/FPT.2005.1568543)**  
C.T. Chow, L.S.M. Tsui, Philip H.W. Leong, Wayne Luk; Steven J.E. Wilton

#### 2004, Brisbane, Australia
**[Directional and Single-Driver Wires in FPGA Interconnect](https://doi.org/10.1109/FPT.2004.1393249)**  
Guy Lemieux; Edmund Lee; Marvin Tom; Anthony Yu

#### 2003, Tokyo, Japan
**[Product Term Embedded Synthesizable Logic Cores](https://doi.org/10.1109/FPT.2003.1275744)**  
Andy Yan and S.J.E. Wilton

[Source](http://www.ee.cityu.edu.hk/~rcheung/FPT/papers.html)