VTR 7.0 Release Announcement
To the FPGA Research Community,
We are pleased to announce the release of VTR 7.0. VTR is an open source framework for FPGA CAD and architecture exploration. The framework includes CAD tools that map Verilog/BLIF circuits to a user defined FPGA, benchmarks from a variety of applications/sources, sample FPGA architecture description files, and scripts that tie these different components together.
What is new in VTR 7.0:
- Basic carry chain support through the whole CAD flow from elaboration down to routing.
- Multi-clock timing analysis with support for simple SDC timing constraints
- Architecture files that describe realistic, complex FPGAs with a reasonable capture of area, delay, and power values
- Post-routed netlist support for timing-driven simulation
- Increased Verilog language support (eg. memory inferencing, support for parameters)
- Verilog simulation and visualization for debugging
- Better quality of results for complex FPGA logic blocks
- Bug fixes and user friendliness improvements (Thank you to all users who provided us feedback on our first release of VTR)
The release may be downloaded here: http://www.eecg.utoronto.ca/vtr/terms.html
The VTR wiki and software trunk may be found here: http://code.google.com/p/vtr-verilog-to-routing/
We hope that VTR will continue to aid your future research on FPGA architecture and CAD.
The VTR Development Team
Source: VTR 7.0 Release Announcement