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ACM SIGDA Technical Committee on FPGAs and Reconfigurable Computing

An FPGA Implementation of Explicit-State Model Checking (2008)
posted by Andre on Sunday April 01, @02:18PM
from the FPGAs-for-Verification dept.
FCCM 20 Nomination wayne writes "The first and probably still the only paper describing how model checking can be accelerated by reconfigurable computing; since verification is becoming a bottleneck in design development, techniques such as the ones described in this paper would become increasingly important."

Title:An FPGA Implementation of Explicit-State Model Checking
DOI Link:

Significance Criteria
[Key Building Block: 2] [Opened Area: 5] [Industry Impact: 2] [Model Paper: 4] [Highly Cited: 1]
(all rated 1 (low=bottom half of all papers in FPGA conference) to 5 (high=in top 5 papers by this criteria);
if you would rate differently, leave a comment with your suggested changes and rationale.)

Rate the article in this nomination
Rate: An FPGA Implementation of Explicit-State Model Checking (2008)
5: should be considered a candidate for top overall paper
4: definitely should be in most significant (definitely in top 10 paper)
3: worthy nomination for consideration (definitely in top 50 papers)
2: good paper (top 50%), but there are plenty of better papers
1: should not be considered (bottom 50%)
No Opinion
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Comments:0 | Votes:1

A MATLAB compiler for distributed, heterogeneous, reconfigurable computing systems (2000) | A dynamically-reconfigurable, power-efficient turbo decoder (2004)  >


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