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ACM SIGDA Technical Committee on FPGAs and Reconfigurable Computing

VPR 5.0
posted by Andre on Thursday October 21, @07:31AM
from the new-and-improved-version-of-classic-tool dept.
Open Source phwl writes "Versatile place and route (VPR) was originally created by Vaughn Betz and Jonathan Rose at the University of Toronto. The goals of VPR were:
  • To support the flexible description and exploration of FPGA architectures
  • Be a platform for CAD tool algorithm exploration and development
  • Support packing, placement and routing of FPGAs

Earlier versions only supported the island-style FPGA model, but the latest version, VPR 5.0, includes support for modern architectural features such as single driver routing and coarse grained blocks. Using VPR, one can place and route a design to estimate its performance. Being open source it can be adapted for modelling new architectures, making it a powerful architectural exploration tool.

A complete Verilog-based open source design flow is available which uses VPR for place and route. In this flow, ODIN, is used for behavioural synthesis. This tool takes Verilog input and creates a netlist. It supports heterogeneous FPGA structures.

The output of ODIN is in the form of a netlist which can be used as input to Berkeley's ABC logic synthesis tool which can optimise the logic and pack it into lookup tables.

The output of ABC is passed to T-VPack which packs registers and lookup tables into clusters, a process called clustering."

Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density (1999) | Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really  >


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